NDLI: Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications

Content Provider	IEEE Xplore Digital Library
Author	Yamada, T. Nakajima, Y. Hanajiri, T. Sugano, T.
Copyright Year	1963
Abstract	In this paper, the authors propose novel metal-oxide-semiconductor field-effect transistor (MOSFET) types featuring additional L-shaped counterdoped areas in the source and/or drain regions of silicon-on-insulator (SOI) MOSFETs to reduce drain-induced barrier lowering (DIBL) through the buried oxide (BOX) layer. The L-shaped region in the drain area shields the BOX layer from penetration by the drain electric field, thereby reducing DIBL in the body region. Simulation of the electrical characteristics of these novel MOSFETs demonstrated more remarkable DIBL suppression and subthreshold slope performance in short-channel regions than in conventional SOI MOSFETs. In addition to this suppression, these novel MOSFETs suppress breakdown voltage more effectively than conventional SOI MOSFETs. The authors concluded that the proposed devices are capable of contributing to the scaling of SOI MOSFETs in ultralarge-scale integration circuits.
Sponsorship	IEEE Electron Devices Society
Starting Page	260
Ending Page	267
Page Count	8
File Size	1285823
File Format	PDF
ISSN	00189383
Volume Number	60
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Body regions Silicon on insulator technology Substrates Threshold voltage Logic gates Scattering silicon on insulator (SOI) Drain-induced barrier lowering (DIBL) impact ionization low operating power metal–oxide–semiconductor field-effect transistor (MOSFET) short-channel effect (SCE)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor

Analysis of gate engineered SOI MOSFET for VLSI application

Corrections to “Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications” [Jan 13 260-267]

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