NDLI: Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry

Content Provider	IEEE Xplore Digital Library
Author	Le, J. Hanken, C. Held, M. Hagedorn, M.S. Mayaram, K. Fiez, T.S.
Copyright Year	1993
Abstract	Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL convention logic (NCL) and traditional clocked Boolean logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 μm process shows that a pseudo-random number generator implemented with NCL generates 23 dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta-sigma modulator (DSM) example. The signal-to-noise ratio performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15 dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	344
Ending Page	356
Page Count	13
File Size	1886713
File Format	PDF
ISSN	10638210
Volume Number	20
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise Substrates Switches Clocks Synchronization Noise measurement Logic gates synchronous circuit Asynchronous circuit delta-sigma modulator (DSM) NULL convention logic (NCL) substrate noise
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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