NDLI: AdNoC: Runtime Adaptive Network-on-Chip Architecture

Content Provider	IEEE Xplore Digital Library
Author	Al Faruque, M.A. Ebi, T. Henkel, J.
Copyright Year	1993
Abstract	Networsk-on-chip (NoCs) have emerged as a promising on-chip interconnect for future multi/many-core architectures as NoCs are able to scale communication links with the growing number of cores. State-of-the-art NoC designs rely mainly on a static network configuration using fixed routing algorithms and buffer placements. These approaches are not effective in dealing with hard-to-predict system behavior, for instance due to user behavior or varying workloads, since in order for static NoCs to cover these scenarios, they would have to be designed for worst case scenarios. In this paper, we address these problems with a runtime adaptive network-on-chip (AdNoC). Focusing on the architecture-level adaptation, we present an adaptive route allocation algorithm which provides a required level of QoS (guaranteed bandwidth) coupled with an adaptive buffer assignment scheme which reassigns buffer blocks on-demand. Furthermore, the adaptivity requires a comprehensive, hardly intrusive, runtime observability infrastructure, i.e., using monitoring components, in order to gather data on the system state. The area overhead introduced by the adaptive scheme can be traded off against the flexibility gained. Moreover, the area overhead is also reduced by resource multiplexing due to the on-demand buffer assignment at each output port (we achieved on an average 42% buffer saving in our experiments). We demonstrate the advantage by using various digital media applications and compare our approach to the state-of-the-art static NoC architectures e.g., Xpipe, QNoC, and Æthereal.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	257
Ending Page	269
Page Count	13
File Size	2916814
File Format	PDF
ISSN	10638210
Volume Number	20
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime Bandwidth Routing System-on-a-chip Computer architecture Observability Adaptive systems quality-of-service (QoS) C.1.3.a adaptable architectures C.1.4.e multicore/single-chip multiprocessors C.1.4.g on-chip interconnection networks network-on-chip (NoC)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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AdNoC: Runtime Adaptive Network-on-Chip Architecture

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