NDLI: Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering

Content Provider	IEEE Xplore Digital Library
Author	Longxing Shi Wei Zhao Jianhui Wu Chao Chen
Copyright Year	2004
Abstract	A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	239
Ending Page	243
Page Count	5
File Size	182104
File Format	PDF
ISSN	15497747
Volume Number	59
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Solid state circuits Capacitors Convergence CMOS integrated circuits Interference Analog circuits pipelined analog-to-digital converter (ADC) Analog-to-digital conversion digital background calibration
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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