NDLI: A Digitally Testable <formula formulatype=inline> <tex Notation=TeX>$Sigma-Delta$</tex></formula> Modulator Using the Decorrelating Design-for-Digital-Testability

Content Provider	IEEE Xplore Digital Library
Author	Sheng-Chuan Liang Hao-Chiao Hong
Copyright Year	1993
Abstract	This paper demonstrates a digitally testable second-order Σ - Δ modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D³T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D³T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ - Δ modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Σ - Δ modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D³T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D³T MUT only consists of 13 switches.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	503
Ending Page	507
Page Count	5
File Size	713918
File Format	PDF
ISSN	10638210
Volume Number	19
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Digital modulation Delta-sigma modulation Decorrelation Finite impulse response filter Switched capacitor networks Switching converters Delay Filtering Noise shaping Sigma-Delta modulation Analog-to-digital conversion (ADC) built-in self-test (BIST) design-for-testability (DfT) integrated circuit testing mixed-mode circuit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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