NDLI: Grid Synchronization PLL Based on Cascaded Delayed Signal Cancellation

Content Provider	IEEE Xplore Digital Library
Author	Yi Fei Wang Yun Wei Li
Copyright Year	1986
Abstract	During the grid synchronization of distributed generation (DG) units, phase-locked loop (PLL) is well accepted as an efficient approach to detect grid phase angle. Conventional PLL schemes used in DG controller have to compromise between steady-state accuracy and transient dynamics when grid voltage is polluted by unbalance and harmonics. To simultaneously realize good steady-state and transient performances, this paper proposes a general delayed signal cancellation (DSC) operator, which can be tailored to eliminate any specified harmonic. The proposed DSC operator can be further cascaded to stepwise reject all undesired harmonics. Then the conditioned voltage signal can be used in PLL loop to achieve fast transient response at high control bandwidth without suffering from the steady-state error caused by harmonics. Based on differently configured DSC operators, two PLL designs are then developed, namely CDSC-PLL1 and CDSC-PLL2. Specifically, CDSC-PLL1 is aimed for grid voltage with unbalance and odd/even harmonics, while CDSC-PLL2 further addresses asymmetrical harmonics, i.e., harmonics arising from asymmetrically distorted three-phase voltages. By introducing a frequency feedback loop, the proposed PLL can operate properly during considerable frequency variations, even when a phase jump or severe harmonics are also present. All proposed PLL designs have very simple structure and can be easily implemented. The superior performance is confirmed by experimental results.
Sponsorship	IEEE Power Electronics Society
Starting Page	1987
Ending Page	1997
Page Count	11
File Size	1573272
File Format	PDF
ISSN	08858993
Volume Number	26
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Harmonic analysis Phase locked loops Power system harmonics Steady-state Frequency control Delay Transient analysis phase-locked loop (PLL) Distributed generation (DG) delayed signal cancellation (DSC) grid synchronization phase detection
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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