NDLI: An Implementation of a Spike-Response Model With Escape Noise Using an Avalanche Diode

Content Provider	IEEE Xplore Digital Library
Author	Clayton, T. Cameron, K. Rae, B.R. Sabatier, N. Charbon, E. Henderson, R.K. Leng, G. Murray, A.
Copyright Year	2007
Abstract	This paper introduces a novel probabilistic spike-response model through the combination of avalanche diode-generated Poisson distributed noise, and a standard exponential decay-based spike-response curve. The noise source, which is derived from a 0.35-μm single-photon avalanche diode (kept in the dark), was tested experimentally to verify its characteristics, before being combined with a field-programmable gate-array implementation of a spike-response model. This simple model was then analyzed, and shown to reproduce seven of eight behaviors recorded during an extensive study of the ventral medial hypothalamic (VMH) region of the brain. It is thought that many of the cell types found within the VMH are fed from a tonic noise synaptic input, where the patterns generated are a product of their spike response and not their interconnection. This paper shows how this tonic noise source can be modelled, and due to the independent nature of the noise sources, provides an avenue for the exploration of networks of noise-fueled neurons, which play a significant role in pattern generation within the brain.
Sponsorship	IEEE Circuits and Systems Society IEEE Engineering in Medicine and Biology Society
Page Count	13
File Size	1836552
Starting Page	231
Ending Page	243
File Format	PDF
ISSN	19324545
Volume Number	5
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise Biomembranes Electric breakdown Neurons Adaptation model Junctions Brain modeling spiking neuron Modelling single-photon avalanche diode (SPAD) spike-response model
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Biomedical Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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