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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Youngcheol Chae Jimin Cheon Seunghyun Lim Minho Kwon Kwisung Yoo Wunki Jung Dong-Hun Lee Seogheon Ham Gunhee Han |
| Copyright Year | 1966 |
| Abstract | This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-μm CMOS process. Measurement results show a RN of 2.4 erms- and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e-·nJ. |
| Sponsorship | IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE |
| Starting Page | 236 |
| Ending Page | 247 |
| Page Count | 12 |
| File Size | 2241197 |
| File Format | |
| ISSN | 00189200 |
| Volume Number | 46 |
| Issue Number | 1 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-01-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Noise Pixel Modulation Clocks Inverters CMOS image sensors Capacitors low noise and wide dynamic range CMOS image sensor column-parallel delta-sigma $(\Delta \Sigma)$ ADC second-order $\Delta \Sigma$ ADC high speed |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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