NDLI: Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing

Content Provider	IEEE Xplore Digital Library
Author	Smith, J.T. Sandow, C. Das, S. Minamisawa, R.A. Mantl, S. Appenzeller, J.
Copyright Year	1963
Abstract	We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laser annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggressively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures.
Sponsorship	IEEE Electron Devices Society
Starting Page	1822
Ending Page	1829
Page Count	8
File Size	583635
File Format	PDF
ISSN	00189383
Volume Number	58
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Doping Tunneling Logic gates Annealing Junctions Performance evaluation ultrathin-body silicon-on-insulator (SOI) Excimer laser annealing (ELA) nanowire tunneling field-effect transistor (NW-TFET) steep-slope transistors
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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