NDLI: A Three-Terminal Dual-Pillar STT-MRAM for High-Performance Robust Memory Applications

Content Provider	IEEE Xplore Digital Library
Author	Mojumder, N.N. Gupta, S.K. Choday, S.H. Nikonov, D.E. Roy, K.
Copyright Year	1963
Abstract	The design of a three-terminal self-aligned dual-pillar (DP) magnetic tunnel junction (MTJ) utilizing both current-induced spin-transfer torque (STT) and magnetic domain-wall motion effects is proposed for high-speed nonvolatile robust memory applications. The choice of a thin tunneling oxide (~0.9 nm) in a write-in port, spatially and electrically separated from a read-out port incorporating a thicker (~1.8 nm) oxide on an extended thin-film multilayer stack, significantly improves the overall cell stability and parametric process yield of a memory array. A dual-bit-line memory architecture incorporating a single-ended voltage-sensing scheme for fast data readout with just one access transistor per cell is also proposed for the first time. The technology-circuit cooptimization of the proposed single-transistor (1T) DP STT magnetic random access memory (MRAM) cell is carried out using effective mass-based transport simulations in nonequilibrium Green's function formalism and accurate micromagnetic simulations involving the Landau-Lifshitz-Gilbert-Slonczewski equation. The proposed DP STT-MRAM bit cell outperforms a state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell tunneling magnetoresistance, simplified memory array architecture with a single supply for read/write, and significantly lower probability of disturb and access failures under parametric process variations with a marginal increase in critical switching current.
Sponsorship	IEEE Electron Devices Society
Starting Page	1508
Ending Page	1516
Page Count	9
File Size	1460053
File Format	PDF
ISSN	00189383
Volume Number	58
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Microprocessors Magnetic tunneling Tunneling magnetoresistance Switches Transistors tunneling magnetoresistance Magnetic domain walls magnetic memory magnetic multilayers magnetization reversal memory architecture nonvolatile memory spin-transfer torque
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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