NDLI: Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error

Content Provider	IEEE Xplore Digital Library
Author	Garofalo, V. Petra, N. Napoli, E.
Copyright Year	1968
Abstract	A truncated multiplier is a multiplier with two n bit operands that produces a n bit result. Truncated multipliers discard some of the partial products of a complete multiplier to trade off accuracy with hardware cost. Compared with a conventional multiplier, a truncated multiplier introduces an error on the output whose magnitude depends on the input bits. The maximum value of the error is hardly computable, since it isn't possible to test every possible input and nonexhaustive simulations are very unlikely to provide the actual maximum absolute error value. It is therefore extremely useful to develop methods that provide the maximum error for a truncated multiplier. This paper presents a closed form analytical calculation, for every bit width, of the maximum error for a previously proposed family of truncated multipliers. The considered family of truncated multipliers is particularly important since it is proved to be the design that gives the lowest mean square error for a given number of discarder partial products. With the contribution of this paper, the considered family of truncated multipliers is the only architecture that can be designed, for every bit width, using an analytical approach that allows the a priori knowledge of the maximum error.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	1366
Ending Page	1371
Page Count	6
File Size	721644
File Format	PDF
ISSN	00189340
Volume Number	60
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuits Mean square error methods Least squares approximation Accuracy Finite wordlength effects Hardware Silicon carbide maximum error. Multiplication truncated multipliers digital arithmetic error compensation error analysis
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

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