NDLI: Multilevel Cache Modeling for Chip-Multiprocessor Systems

Please wait, while we are loading the content...

Multilevel Cache Modeling for Chip-Multiprocessor Systems

Content Provider	IEEE Xplore Digital Library
Author	Prieto, P. Puente, V. Gregorio, J.-A.
Copyright Year	2002
Abstract	This paper presents a simple analytical model for predicting on-chip cache hierarchy effectiveness in chip multiprocessors (CMP) for a state-of-the-art architecture. Given the complexity of this type of systems, we use rough approximations, such as the empirical observation that the re-reference timing pattern follows a power law and the assumption of a simplistic delay model for the cache, in order to provide a useful model for the memory hierarchy responsiveness. This model enables the analytical determination of average access time, which makes design space pruning useful before sweeping the vast design space of this class of systems. The model is also useful for predicting cache hierarchy behavior in future systems. The fidelity of the model has been validated using a state-of-the-art, full-system simulation environment, on a system with up to sixteen out-of-order processors with cache-coherent caches and using a broad spectrum of applications, including complex multithread workloads. This simple model can predict a near-to-optimal, on-chip cache distribution while also estimating how future system running future applications might behave.
Starting Page	49
Ending Page	52
Page Count	4
File Size	450682
File Format	PDF
ISSN	15566056
Volume Number	10
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thermal analysis Cache storage Complexity theory Computational modeling Thermal sensors Software tools Multiprocessing systems Memory hierarchy Multi-core/single-chip multiprocessors
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems

SkipCache: application aware cache management for chip multi-processors

Nahalal: Cache Organization for Chip Multiprocessors

Cache Hierarchy Optimization

CPU Accounting in CMP Processors

On Supporting Rapid Thermal Analysis

Performance Effects of a Cache Miss Handling Architecture in a Multi-core Processor

Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems

Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs

Multilevel Cache Modeling for Chip-Multiprocessor Systems

Similar Documents

Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems

SkipCache: application aware cache management for chip multi-processors

Nahalal: Cache Organization for Chip Multiprocessors

Cache Hierarchy Optimization

CPU Accounting in CMP Processors

On Supporting Rapid Thermal Analysis

Performance Effects of a Cache Miss Handling Architecture in a Multi-core Processor

Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems

Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs

Multilevel Cache Modeling for Chip-Multiprocessor Systems