NDLI: Generalized Pipelined Tomlinson–Harashima Precoder Design Methodology With Build-In Arbitrary Speed-Up Factors

Content Provider	IEEE Xplore Digital Library
Author	Yen-Liang Chen An-Yeu Wu
Copyright Year	1991
Abstract	In Tomlinson-Harashima (TH) precoding, the feedback filter (FBF) of a decision feedback equalizer (DFE) and the modulo devices are implemented at the transmitter. Because the TH precoders contain nonlinear feedback loops, it restricts their development for high-speed applications. With very large output levels of the modulo devices in the TH precoders, it is difficult to apply look-ahead and precomputation techniques to pipeline the TH precoders which are usually useful to pipeline IIR filters and DFEs. Among existing works of high-speed TH precoder designs, Gu and Parhi derived two pipelined TH precoder designs (PIPTHP1, 2). The architectures of these two designs seem to be very different and have their-own pros and cons. In this paper, we propose a two-time pipelining scheme to pipeline the TH precoders, which enables us to develop a generalized TH precoder architecture. PIPTHP1 and PIPTHP2 are derived by only applying the first-time and second-time pipelining schemes, respectively. Hence, both the designs can be considered as two extreme cases of the proposed designs. In conclusion, for a given design specification, the proposed scheme can provide tradeoffs between hardware complexity and output dynamic range, which leads to a near-optimal solution based on these design criteria. Therefore, the proposed scheme provides more degrees of freedom for the design trade-offs of high-speed pipelining TH precoders with build-in arbitrary speedup factors.
Sponsorship	IEEE Signal Processing Society
Starting Page	2375
Ending Page	2382
Page Count	8
File Size	664782
File Format	PDF
ISSN	1053587X
Volume Number	58
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design methodology Pipeline processing IIR filters Parity check codes Decision feedback equalizers Feedback loop Hardware Dynamic range Quadrature amplitude modulation Transmitters Tomlinson-Harashima precoding (THP) High speed look-ahead pipelining
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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