NDLI: Robust Register Caching: An Energy-Efficient Circuit-Level Technique to Combat Soft Errors in Embedded Processors

Content Provider	IEEE Xplore Digital Library
Author	Fazeli, M. Namazi, A. Miremadi, S.G.
Copyright Year	2001
Abstract	This paper presents a cost-efficient technique to jointly use circuit- and architecture-level techniques to protect an embedded processor's register file against soft errors. The basic idea behind the proposed technique is robust register caching (RRC), which creates a cache of the most vulnerable registers within the register file in a small and highly robust cache memory built from circuit-level single-event-upset-protected memory cells. To guarantee that the most vulnerable registers are always stored in the robust register cache, the average number of read operations during a register's lifetime is used as a metric to guide the cache replacement policy. A register is vulnerable to soft errors when it holds a value that will be used in subsequent cycles. Consequently, while a register value is stored in the register cache, it is robust against single- and multiple-bit upsets. To minimize the power overhead of the RRC, the clock-gating technique is efficiently exploited by the main register file, resulting in significantly reduced power consumption. The RRC was experimentally evaluated using the LEON processor for two benchmarks, namely, the MiBench embedded benchmark suite and the SPEC CPU2006 general-purpose benchmark. Our experimental results show that if the cache size is selected appropriately, the architectural vulnerability factor (AVF) of the register file is significantly reduced while also offering the benefits of low power, area, and performance overheads.
Sponsorship	IEEE Electron Devices Society IEEE Reliability Society
Starting Page	208
Ending Page	221
Page Count	14
File Size	1148108
File Format	PDF
ISSN	15304388
Volume Number	10
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robustness Registers Energy efficiency Circuits Protection Energy consumption Error correction codes Random access memory Cache memory Clocks single-event upset (SEU) Embedded processors fault tolerance multiple-bit upsets (MBUs) register file
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Safety, Risk, Reliability and Quality Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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