NDLI: Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors

Content Provider	IEEE Xplore Digital Library
Author	Kwen-Siong Chong Kok-Leong Chang Bah-Hwee Gwee Chang, J.S.
Copyright Year	1966
Abstract	We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal V_DD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery (V_DD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at V_DD = 1.2 V, it dissipates 186 μW.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	769
Ending Page	780
Page Count	12
File Size	2129060
File Format	PDF
ISSN	00189200
Volume Number	47
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Synchronization Clocks Batteries System-on-a-chip Acoustic signal detection Protocols dynamic voltage scaling Asynchronous-logic synchronous-logic low power GALS
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

A Fine-Grain Variation-Aware Dynamic ${rm Vdd}$-Hopping AVFS Architecture on a 32 nm GALS MPSoC

High Rate Data Synchronization in GALS SoCs

A 167-Processor Computational Platform in 65 nm CMOS

AsAP: An Asynchronous Array of Simple Processors

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

A Trace-Based Framework for Verifiable GALS Composition of IPs

Power Management of Voltage/Frequency Island-Based Systems Using Hardware-Based Methods

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors

Similar Documents

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

A Fine-Grain Variation-Aware Dynamic ${rm Vdd}$-Hopping AVFS Architecture on a 32 nm GALS MPSoC

High Rate Data Synchronization in GALS SoCs

A 167-Processor Computational Platform in 65 nm CMOS

AsAP: An Asynchronous Array of Simple Processors

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

A Trace-Based Framework for Verifiable GALS Composition of IPs

Power Management of Voltage/Frequency Island-Based Systems Using Hardware-Based Methods

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors