NDLI: A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply

Content Provider	IEEE Xplore Digital Library
Author	Chan, W.L. Long, J.R.
Copyright Year	1966
Abstract	A 60-GHz band, three-stage pseudo-differential power amplifier (PA) is implemented with input and output baluns on-chip. Each stage consists of a neutralized common-source amplifier pair. Neutralization mitigates the intrinsic gate-drain feedback of each transistor for increased power gain and reverse isolation. Shielded transformers couple the gain stages and allow low supply voltage operation. Fabricated in a 65-nm bulk CMOS process, the measured small-signal gain of the 0.13 × 0.41 mm² PA is 16 dB at 60 GHz with 3-dB bandwidth more than 8.5 GHz, while consuming 50 mW from a 1-V supply. Reverse isolation is better than 42 dB from 55 to 65 GHz. Maximum saturated output power is 11.5 dBm with a peak PAE of 15.2% measured at 62 GHz; from 58 to 65 GHz, the measured PAE is above 10%.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	554
Ending Page	564
Page Count	11
File Size	1559180
File Format	PDF
ISSN	00189200
Volume Number	45
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power amplifiers Power measurement Impedance matching Feedback Transformers Low voltage CMOS process Gain measurement Bandwidth Power generation low supply voltage CMOS millimeter-wave transformer-coupling balun differential shielding power amplifier neutralization broadband
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A two-stage mm-wave PA with 18.5% PAE in 65 nm CMOS

A 60 GHz transformer-based variable-gain power amplifier in 90nm CMOS

Design of 60-GHz amplifiers based on over neutralization and optimized inter-stage matching networks in 65-nm CMOS

A 5 GHz Low Noise Amplifier with On-Chip Transformer-Balun

A 5 GHz Low Noise Amplifier with On-Chip Transformer-Balun

Design of a high gain power amplifier for 77 GHz radar automotive applications in 65-nm CMOS

A 65 nm CMOS Power Amplifier With Peak PAE above 18.9% From 57 to 66 GHz Using Synthesized Transformer-Based Matching Network

A 21.08 dBm Q-band power amplifier in 90-nm CMOS process

A 16.4-dBm 20.3% PAE 22-dB Gain 77 GHz Power Amplifier in 65-nm CMOS Technology

A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply

Similar Documents

A two-stage mm-wave PA with 18.5% PAE in 65 nm CMOS

A 60 GHz transformer-based variable-gain power amplifier in 90nm CMOS

Design of 60-GHz amplifiers based on over neutralization and optimized inter-stage matching networks in 65-nm CMOS

A 5 GHz Low Noise Amplifier with On-Chip Transformer-Balun

A 5 GHz Low Noise Amplifier with On-Chip Transformer-Balun

Design of a high gain power amplifier for 77 GHz radar automotive applications in 65-nm CMOS

A 65 nm CMOS Power Amplifier With Peak PAE above 18.9% From 57 to 66 GHz Using Synthesized Transformer-Based Matching Network

A 21.08 dBm Q-band power amplifier in 90-nm CMOS process

A 16.4-dBm 20.3% PAE 22-dB Gain 77 GHz Power Amplifier in 65-nm CMOS Technology

A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply