NDLI: A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology

Content Provider	IEEE Xplore Digital Library
Author	Song-Yu Yang Wei-Zen Chen Tai-You Lu
Copyright Year	1966
Abstract	A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simultaneously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 ¿s locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1 mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm ².
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	578
Ending Page	586
Page Count	9
File Size	2021581
File Format	PDF
ISSN	00189200
Volume Number	45
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Frequency synthesizers Digital filters Semiconductor device measurement Computerized monitoring Tracking loops Bandwidth Power dissipation Timing Time measurement bang-bang phase detector ADPLL phase-locked loop phase accumulator frequency divider phase-frequency detector
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 5 GHz, 32 mW CMOS frequency synthesizer with an injection locked frequency divider

A 40-GHz Frequency Divider in 90-nm CMOS Technology

A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

A 35-GHz frequency synthesizer using frequency doubling and phase rotating technology

A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients

A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS

A 3.4-mW 2.4-GHz frequency synthesizer in 0.18 µm CMOS

A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology

Similar Documents

A 5 GHz, 32 mW CMOS frequency synthesizer with an injection locked frequency divider

A 40-GHz Frequency Divider in 90-nm CMOS Technology

A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

A 35-GHz frequency synthesizer using frequency doubling and phase rotating technology

A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients

A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS

A 3.4-mW 2.4-GHz frequency synthesizer in 0.18 µm CMOS

A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology