NDLI: A Comprehensive Understanding of the Efficacy of N-Ring SEE Hardening Methodologies in SiGe HBTs

Content Provider	IEEE Xplore Digital Library
Author	Phillips, S.D. Moen, K.A. Najafizadeh, L. Diestelhorst, R.M. Sutton, A.K. Cressler, J.D. Vizkelethy, G. Dodd, P.E. Marshall, P.W.
Copyright Year	1963
Abstract	We investigate the efficacy of mitigating radiation-based single event effects (SEE) within circuits incorporating SiGe heterojunction bipolar transistors (HBTs) built with an N-Ring, a transistor-level layout-based radiation hardened by design (RHBD) technique. Previous work of single-device ion-beam induced charge collection (IBICC) studies has demonstrated significant reductions in peak collector charge collection and sensitive area for charge collection; however, few circuit studies using this technique have been performed. Transient studies performed with Sandia National Laboratory's (SNL) 36 MeV ¹⁶O microbeam on voltage references built with N-Ring SiGe HBTs have shown mixed results, with reductions in the number of large voltage disruptions in addition to new sensitive areas of low-level output voltage disturbances. Similar discrepancies between device-level IBICC results and circuit measurements are found for the case of digital shift registers implemented with N-Ring SiGe HBTs irradiated in a broadbeam environment at Texas A&M's Cyclotron Institute. The error cross-section curve of the N-Ring based register is found to be larger at larger ion LETs than the standard SiGe register, which is clearly counter-intuitive. We have worked to resolve the discrepancy between the measured circuit results and the device-level IBICC measurements, by re-measuring single-device N-Ring SiGe HBTs using a time-resolved ion beam induced charge (TRIBIC) set-up that allows direct capture of nodal transients. Coupling these measurements with full 3-D TCAD simulations provides complete insight into the origin of transient currents in an N-Ring SiGe HBT. The detailed structure of these transients and their bias dependencies are discussed, together with the ramifications for the design of space-borne analog and digital circuits using SiGe HBTs.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	3400
Ending Page	3406
Page Count	7
File Size	1011198
File Format	PDF
ISSN	00189499
Volume Number	57
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Single event upset Silicon germanium Radiation hardening Heterojunction bipolar transistors silicon-germanium technology HBT N-ring hardening RHBD SEE SEU SiGe
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

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Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits

3-D Simulation of SEU Hardening of SiGe HBTs Using Shared Dummy Collector

Single-Event Response of the SiGe HBT Operating in Inverse-Mode

Non-TMR SEU-Hardening Techniques for SiGe HBT Shift Registers and Clock Buffers

An Evaluation of Transistor-Layout RHBD Techniques for SEE Mitigation in SiGe HBTs

A Novel Device Architecture for SEU Mitigation: The Inverse-Mode Cascode SiGe HBT

Design of Digital Circuits Using Inverse-Mode Cascode SiGe HBTs for Single Event Upset Mitigation

A Novel Circuit-Level SEU Hardening Technique for High-Speed SiGe HBT Logic Circuits

A Mechanism Versus SEU Impact Analysis of Collector Charge Collection in SiGe HBT Current Mode Logic

A Comprehensive Understanding of the Efficacy of N-Ring SEE Hardening Methodologies in SiGe HBTs

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Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits

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