NDLI: Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Guojun Zhu Xing Zhou Yoke-King Chin Kin Leong Pey Junbin Zhang Guan Huei See Shihuan Lin Yafei Yan Zuhui Chen
Copyright Year	1963
Abstract	In this paper, we demonstrate analytical device models and a unique subcircuit approach to physically and accurately model the dopant-segregated Schottky (DSS) gate-all-around (GAA) Si-nanowire (SiNW) MOSFETs. The direct current characteristics of the DSS GAA SiNW MOSFETs are investigated through numerical simulations and fabricated devices. Transport mechanisms are studied and explained with numerical devices from ambipolar thermionic tunneling to unipolar drift-diffusion and a combination of both as the dopant segregation doping and thickness are varied. The convex curvature in the I_ds- V_ds characteristics is accurately reproduced by the subcircuit compact model, and it is shown for the first time that such a unique g_ds-V_ds characteristic in DSS devices is only feasible to be modeled by the subcircuit approach.
Sponsorship	IEEE Electron Devices Society
Starting Page	772
Ending Page	781
Page Count	10
File Size	1622567
File Format	PDF
ISSN	00189383
Volume Number	57
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Decision support systems Logic gates Numerical models Leakage current Semiconductor process modeling Mathematical model unipolar Ambipolar compact model dopant-segregated Schottky (DSS) drift–diffusion (DD) gate-all-around (GAA) gate-induced drain leakage (GIDL) MOSFET Schottky barrier (SB) subcircuit thermionic tunneling (TT)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Compact Model for Undoped Silicon-Nanowire MOSFETs With Schottky-Barrier Source/Drain

Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels

Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering

A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs

Dopant-Segregated Schottky Source/Drain FinFET With a NiSi FUSI Gate and Reduced Leakage Current

A Compact Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs. Part I: DC Characteristics

III-V Junctionless Gate-All-Around Nanowire MOSFETs for High Linearity Low Power Applications

Analysis of Transconductance $(g_{m})$ in Schottky-Barrier MOSFETs

Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In_0.53Ga_0.47As GAA MOSFET

Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs

Similar Documents

A Compact Model for Undoped Silicon-Nanowire MOSFETs With Schottky-Barrier Source/Drain

Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels

Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering

A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs

Dopant-Segregated Schottky Source/Drain FinFET With a NiSi FUSI Gate and Reduced Leakage Current

A Compact Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs. Part I: DC Characteristics

III-V Junctionless Gate-All-Around Nanowire MOSFETs for High Linearity Low Power Applications

Analysis of Transconductance $(g_{m})$ in Schottky-Barrier MOSFETs

Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In0.53Ga0.47As GAA MOSFET

Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs

Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In_0.53Ga_0.47As GAA MOSFET