NDLI: A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment

Content Provider	IEEE Xplore Digital Library
Author	Benkrid, K. Ying Liu Benkrid, A.
Copyright Year	1993
Abstract	This paper presents the design and implementation of the most parameterisable field-programmable gate array (FPGA)-based skeleton for pairwise biological sequence alignment reported in the literature. The skeleton is parameterised in terms of the sequence symbol type, i.e., DNA, RNA, or protein sequences, the sequence lengths, the match score, i.e., the score attributed to a symbol match, mismatch or gap, and the matching task, i.e., the algorithm used to match sequences, which includes global alignment, local alignment, and overlapped matching. Instances of the skeleton implement the Smith-Waterman and the Needleman-Wunsch algorithms. The skeleton has the advantage of being captured in the Handel-C language, which makes it FPGA platform-independent. Hence, the same code could be ported across a variety of FPGA families. It implements the sequence alignment algorithm in hand using a pipeline of basic processing elements, which are tailored to the algorithm parameters. This paper presents a number of optimizations built into the skeleton and applied at compile-time depending on the user-supplied parameters. These result in high performance FPGA implementations tailored to the algorithm in hand. For instance, actual hardware implementations of the Smith-Waterman algorithm for Protein sequence alignment achieve speedups of two orders of magnitude compared to equivalent standard desktop software implementations.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	561
Ending Page	570
Page Count	10
File Size	1011617
File Format	PDF
ISSN	10638210
Volume Number	17
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Skeleton Sequences Field programmable gate arrays Biological information theory DNA RNA Proteins Pipelines Hardware Software algorithms Xilinx Virtex-II Biological sequence alignment field-programmable gate array (FPGA) Handel-C Needleman–Wunsch Smith–Waterman
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

High-Performance and Dynamically Updatable Packet Classification Engine on FPGA

Single event analysis and fault injection techniques targeting complex designs implemented in xilinx-virtex family field programmable gate array (fpga) devices

Development and Implementation of Parameterized FPGA-Based General Purpose Neural Networks for Online Applications

A Reconfigurable Accelerator for Smith–Waterman Algorithm

Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

An FPGA Implementation of Frequency Output

A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment

Similar Documents

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

High-Performance and Dynamically Updatable Packet Classification Engine on FPGA

Single event analysis and fault injection techniques targeting complex designs implemented in xilinx-virtex family field programmable gate array (fpga) devices

Development and Implementation of Parameterized FPGA-Based General Purpose Neural Networks for Online Applications

A Reconfigurable Accelerator for Smith–Waterman Algorithm

Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

An FPGA Implementation of Frequency Output

A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment