NDLI: A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing

Content Provider	IEEE Xplore Digital Library
Author	Ito, K. Tongprasit, B. Shibata, T.
Copyright Year	2004
Abstract	In this paper, a computational digital pixel sensor (DPS) equipped with an on-chip image-processing capability has been developed. In order to resolve the interconnection bottleneck between the sensor array and on-chip processing units, a new block-readout architecture has been proposed and implemented on the chip. The data from the sensor array are read out in a form of a pixel block compatible to kernel image processing, and they are processed in parallel by on-chip processing units. Such an architecture has enabled us to carry out an efficient kernel processing using a linear array of single-instruction-multiple-data processing units. In order to demonstrate the advantage of such an architecture, a rank-order filtering circuit has been implemented on the chip as a case study of the on-chip image processing. In this paper, a binary-search rank-order filtering algorithm has been implemented in a simple circuitry. A proof-of-concept chip having an array of 64 times 48 pixels was designed and fabricated using a 0.35-mum CMOS technology, and the concept has been verified by the measuremet of fabricated chips.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	114
Ending Page	123
Page Count	10
File Size	2580969
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pixel Image sensors Computer architecture Image processing Sensor arrays Kernel CMOS technology Integrated circuit interconnections Filtering algorithms Semiconductor device measurement rank-order filtering CMOS imager computational image sensor digital pixel sensor (DPS)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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