NDLI: Error Propagation Algorithm for Reduction of Errors Due to Total Load and Line Load in a Plasma Panel Display

Content Provider	IEEE Xplore Digital Library
Author	Jin-Sung Kim Hyuk-Jae Lee
Copyright Year	1991
Abstract	The displayed gray level of a plasma display panel (PDP) is often different from the intended target gray level because the displayed level is affected by the load of the panel. The effect of the load on the displayed gray level is decomposed into three factors: total load; line load magnitude; and line load distribution. Previous attempts to reduce this difference (i.e., error) have achieved only limited success because they have not taken three factors into consideration altogether. This paper proposes a new method that compensates for the error caused by all three factors. The proposed method first attempts to compensate for the error caused by line load magnitude and distribution. To this end, the error generated by one sub-field of a PDP is propagated to and compensated for by the remaining sub-fields. The amount of the error is reduced for every incidence of error propagation and, consequently, the final amount of error is reduced to a negligible level. To reduce the computational complexity for the evaluation of the amount of the error caused by the line load distribution, an iterative method is proposed to derive the effect of line load distribution on each cell from its adjacent cell. When sub-field coding is completed for a whole cells on a panel, total load of each sub-field is obtained and the error caused by total load is compensated for by controlling the number of sustain pulses for each sub-field. A significant error reduction is achieved, which shown by simulations and experiments with a 42-in. PDP set, including 91.2% reduction of the mean absolute error obtained through simulations and 69.7% reduction of luminance variation range caused by the load variation in experiments.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	561
Ending Page	573
Page Count	13
File Size	1564077
File Format	PDF
ISSN	10518215
Volume Number	19
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Plasma displays Load management Image quality Voltage Computational complexity Iterative methods Error correction TV Computer science Electrodes sub-field coding Error reduction load distribution load magnitude luminance error plasma display panel (PDP)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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