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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Meher, P.K. |
| Copyright Year | 1982 |
| Abstract | In this paper, we present a new approach for the extension of sequential logic functionality of D flip-flop in order to perform an additional Boolean function simultaneously along with its usual bit-storage function. We show that a combinational function of the form (a middotb), (a + b) , (a +[(b)]), or ([(a)] middotb) which occurs frequently in a feedforward path with a D flip-flop could be implemented efficiently by a D flip-flop with RESET or SET provision. Similarly, (a oplusb) or ((a middotb) oplusc) in the feedback loop with a D flip-flop could be implemented by a T flip-flop by suitable modification of the clock. The use of such extended sequential logic is found to result in a significant reduction in critical path and saving in area complexity over the direct implementation. Moreover, we present a simple approach for the construction of CMOS T flip-flop by modification of clock signal of D flip-flop, which is found to be more efficient than the T flip-flop derived from JK flip-flop. The extended sequential logic is used for the implementation of finite-field multiplication over GF(2m) and carry-save addition of real numbers. In both these cases, the use of extended logic is found to offer a substantial saving in area and time complexity over the conventional implementations. |
| Sponsorship | IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society |
| Starting Page | 469 |
| Ending Page | 477 |
| Page Count | 9 |
| File Size | 517921 |
| File Format | |
| ISSN | 02780070 |
| Volume Number | 28 |
| Issue Number | 4 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Sequential circuits Circuit optimization Flip-flops Feedback loop Boolean functions Clocks CMOS logic circuits Digital arithmetic Digital circuits Registers sequential logic Carry-save addition combinational logic digital arithmetic finite-field arithmetic logic optimization |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software |
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