NDLI: A Controller Area Network Bus Transceiver Behavioral Model for Network Design and Simulation

Content Provider	IEEE Xplore Digital Library
Author	Prodanov, W. Valle, M. Buzas, R.
Copyright Year	1982
Abstract	The main purpose of this paper is to develop reliable and affordable tools and methodologies for the design, simulation, and fault analysis of controller area network (CAN) bus networks. In this paper, a behavioral model of a CAN bus transceiver is proposed and experimentally verified. Moreover, we developed a methodology to efficiently manage the trade-off concerning accuracy, simulation speed, and convergence issues which are usually involved in the simulation of large CAN bus networks. To this aim, three different architectures of the transceiver behavioral model have been implemented: They can be selected by the user to address specific requirements of intended analyses. The architectures are based on a set of behavioral models of the basic mixed-signal circuit building blocks of the transceiver. The models were implemented using the VHDL-AMS language. Signal integrity, fault analysis, power consumption analysis, corner analysis, etc., can be effectively and reliably implemented. Simulation and experimental results, which demonstrate our approach efficiency, are reported.
Sponsorship	IEEE Industrial Electronics Society
Starting Page	3762
Ending Page	3771
Page Count	10
File Size	1388877
File Format	PDF
ISSN	02780046
Volume Number	56
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transceivers Signal analysis Analytical models Circuit faults Circuit simulation Circuit analysis Automotive engineering Fault diagnosis Prototypes Costs VHDL-AMS Behavioral modeling and simulation CAN bus transceivers and networks Controller Area Network (CAN) fault simulation and analysis mixed-signal integrated circuits signal integrity analysis
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering Computer Science Applications

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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