NDLI: A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V<formula formulatype=inline><tex Notation=TeX>$_{min}$</tex></formula> Lowering Techniques and Deep Sleep Mode

Content Provider	IEEE Xplore Digital Library
Author	Tae-Hyoung Kim Liu, J. Kim, C.H.
Copyright Year	1966
Abstract	A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower V_min to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1785
Ending Page	1795
Page Count	11
File Size	1821460
File Format	PDF
ISSN	00189200
Volume Number	44
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Random access memory Leakage current Energy consumption CMOS process Current supplies Circuit stability Pulse circuits Space vector pulse width modulation Automatic control sleep mode Bitline leakage compensation floating bitlines low-voltage SRAM design minimum operation voltage
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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