NDLI: A Slew Controlled LVDS Output Driver Circuit in 0.18 <formula formulatype=inline><tex Notation=TeX>$mu$</tex></formula>m CMOS Technology

Content Provider	IEEE Xplore Digital Library
Author	Tajalli, A. Leblebici, Y.
Copyright Year	1966
Abstract	This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 mum CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 Omega resistor with an output voltage swing of V_OD = 400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm² and the measured output jitter is sigma_rms = 4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load RC time constant.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	538
Ending Page	548
Page Count	11
File Size	1205345
File Format	PDF
ISSN	00189200
Volume Number	44
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Driver circuits Capacitance CMOS technology Impedance Voltage control Low voltage Resistors Power dissipation Area measurement Jitter source-coupled logic (SCL) CMOS integrated circuits current-mode logic (CML) low-voltage differential signaling (LVDS) output driver
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

Power-Aware Design of Nanometer MCML Tapered Buffers

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$mu$m CMOS Technology

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

Low-voltage low-power LVDS drivers

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology

Similar Documents

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

Power-Aware Design of Nanometer MCML Tapered Buffers

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$mu$m CMOS Technology

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

Low-voltage low-power LVDS drivers

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology