NDLI: New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

Content Provider	IEEE Xplore Digital Library
Author	Chung-Yun Cheng Yean-Kuen Fang Jang-Cheng Hsieh Sheng-Jier Yang Yi-Ming Sheu Hsia, H.
Copyright Year	1963
Abstract	Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.
Sponsorship	IEEE Electron Devices Society
Starting Page	1618
Ending Page	1623
Page Count	6
File Size	1023475
File Format	PDF
ISSN	00189383
Volume Number	56
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon germanium Stress Logic gates Distance measurement MOSFET circuits Silicon Layout STI Dummy gate $I_{\rm dlin}$ $I_{\rm dsat}$ length of thin oxide definition area (LOD) effect SiGe source/drain (S/D)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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