NDLI: An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics

Content Provider	IEEE Xplore Digital Library
Author	Yoshikawa, T. Hirata, T. Ebuchi, T. Iwata, T. Arima, Y. Yamauchi, H.
Copyright Year	1993
Abstract	This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction (-19 dB to the non-SSC situation) and a small core area of 0.25 mm² in 0.13-mum CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm². Moreover, it achieved good jitter tolerance (flat 0.8 UI at >1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	1187
Ending Page	1198
Page Count	12
File Size	2250073
File Format	PDF
ISSN	10638210
Volume Number	16
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transceivers System-on-a-chip Consumer electronics Clocks Phase locked loops Data communication Jitter Spread spectrum communication Streaming media Frequency modulation transceivers Adaptive equalizers (AEQ) clock data recovery (CDR) phase interpolator spread spectrum clocking (SSC)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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