NDLI: Fast Elliptic Curve Cryptography on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Chelton, W.N. Benaissa, M.
Copyright Year	1993
Abstract	This paper details the design of a new high-speed pipelined application-specific instruction set processor (ASIP) for elliptic curve cryptography (ECC) using field-programmable gate-array (FPGA) technology. Different levels of pipelining were applied to the data path to explore the resulting performances and find an optimal pipeline depth. Three complex instructions were used to reduce the latency by reducing the overall number of instructions, and a new combined algorithm was developed to perform point doubling and point addition using the application specific instructions. An implementation for the United States Government National Institute of Standards and Technology-recommended curve over GF(2¹⁶³) is shown, which achieves a point multiplication time of 33.05 s at 91 MHz on a Xilinx Virtex-E FPGA-the fastest figure reported in the literature to date. Using the more modern Xilinx Virtex-4 technology, a point multiplication time of 19.55 s was achieved, which translates to over 51120 point multiplications per second.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	198
Ending Page	205
Page Count	8
File Size	420583
File Format	PDF
ISSN	10638210
Volume Number	16
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Elliptic curve cryptography Field programmable gate arrays Pipeline processing Hardware Application specific processors Arithmetic Delay NIST Public key cryptography Clocks pipelining Complex instruction set efficient hardware implementation elliptic curve cryptography (ECC) field-programmable gate array (FPGA)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA

Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves

Design of flexible GF(2/sup m/) elliptic curve cryptography processors

On Parallelization of High-Speed Processors for Elliptic Curve Cryptography

A High-Speed FPGA Implementation of an RSD-Based ECC Processor

Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed

Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations

Lightweight Architecture for Elliptic Curve Scalar Multiplication over Prime Field

High-Performance Implementation of Point Multiplication on Koblitz Curves

Fast Elliptic Curve Cryptography on FPGA

Similar Documents

Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA

Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves

Design of flexible GF(2/sup m/) elliptic curve cryptography processors

On Parallelization of High-Speed Processors for Elliptic Curve Cryptography

A High-Speed FPGA Implementation of an RSD-Based ECC Processor

Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed

Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations

Lightweight Architecture for Elliptic Curve Scalar Multiplication over Prime Field

High-Performance Implementation of Point Multiplication on Koblitz Curves

Fast Elliptic Curve Cryptography on FPGA