NDLI: A Novel DCXO Module for Clock Synchronization in MPEG2 Transport System

Content Provider	IEEE Xplore Digital Library
Author	Liming Xiu
Copyright Year	2004
Abstract	This paper presents a unique on-chip digital control crystal oscillator (DCXO) module that is used for clock synchronization in MPEG2 data transport system. This module is built inside a phase-locked loop (PLL) and is achieved through flying-adder frequency synthesis architecture. It is designed at 27 MHz with a tuning range of plusmn10 kHz. The linearity at the range of 27 MHz plusmn10 kHz is measured as 0.001%. The frequency resolution is 1.6 Hz. This DCXO and its associated PLL consume 10 mW and occupies 0.15 mm² in a 90-nm CMOS process. The contribution of this work is that this built-in DCXO can completely eliminate the need of external voltage-control crystal oscillator (VCXO) chip or on-chip VCXO block in MPEG2 clock synchronization and thus significantly reduces the system cost. This module has been used in a real HDTV SoC chip.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2226
Ending Page	2237
Page Count	12
File Size	1463469
File Format	PDF
ISSN	15498328
Volume Number	55
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Frequency synchronization Phase locked loops System-on-a-chip Voltage-controlled oscillators Digital control Digital-controlled oscillators Frequency synthesizers Control system synthesis Tuning voltage-control crystal oscillator (VCXO) Clock recovery clock synchronization digital control crystal oscillator (DCXO) flying adder MPEG2 phase-locked loop (PLL) PLL VCXO DCXO Flying-Adder clock recovery
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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