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Content Provider | IEEE Xplore Digital Library |
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Author | Yao-Hsin Chou I-Ming Tsai Sy-Yen Kuo |
Copyright Year | 2002 |
Abstract | Recently, a systematic procedure was proposed to derive a minimum input quantum circuit for any given classical logic with the generalized quantum Toffoli gate, which is universal in Boolean logic. Since quantum Boolean circuits are reversible, we can apply this property to build quantum iterative logic array (QILA). QILA can be easily tested in constant time (C-testable) if stuck-at fault model is assumed. In this paper, we use Hadamard and general controlled-controlled not gates to make QILA 1-testable. That is, for any quantum Boolean circuit, the number of test patterns is independent of both the size of the array and the length of the inputs. |
Sponsorship | IEEE Nanotechnology Council |
Starting Page | 484 |
Ending Page | 492 |
Page Count | 9 |
File Size | 466238 |
File Format | |
ISSN | 1536125X |
Volume Number | 7 |
Issue Number | 4 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2008-07-01 |
Publisher Place | U.S.A. |
Access Restriction | One Nation One Subscription (ONOS) |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Circuit testing Logic arrays Logic circuits Circuit faults Quantum computing Boolean functions Design for testability Nanostructures Logic design Logic testing reversible circuit C-testable design for testability (DFT) iterative logic array (ILA) M-testable quantum circuit quantum computation Iterative logic array (ILA) |
Content Type | Text |
Resource Type | Article |
Subject | Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications |
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