NDLI: Design and Implementation of the POWER6 Microprocessor

Content Provider	IEEE Xplore Digital Library
Author	Stolt, B. Mittlefehldt, Y. Dubey, S. Mittal, G. Lee, M. Friedrich, J. Fluhr, E.
Copyright Year	1966
Abstract	The IBM POWER6 processor is a dual-core, 341 mm², 790 million transistor chip fabricated using IBM's 65 nm partially-depleted SOI process. Capable of running at frequencies up to 5 GHz in high performance applications, it can also operate under 100 W for power-sensitive applications. Traditional power-intensive and deep-pipelining techniques used in high frequency design were abandoned in favor of more power efficient circuit design methodologies. The complexity and size of POWER6, together with its high operating frequency, presented a number of significant challenges for its multi-site team to complete the design on an aggressive schedule. This paper describes some of the circuit methodology and implementation innovations used in the development of POWER6, with particular emphasis on custom, synthesized, register file and SRAM design, as well as the electrical characterizations performed in the lab.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	21
Ending Page	28
Page Count	8
File Size	2392448
File Format	PDF
ISSN	00189200
Volume Number	43
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Clocks Frequency Registers Latches Circuit synthesis Pipelines Random access memory Power system protection Logic arrays timing ABIST array circuit design methodology clocking custom circuits dual-core latch LBIST microprocessor power POWER6 register file RLM methodology 65 nm SOI process SRAM
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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