NDLI: 2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

Content Provider	IEEE Xplore Digital Library
Author	Kawahara, T. Takemura, R. Miura, K. Hayakawa, J. Ikeda, S. Young Min Lee Sasaki, R. Goto, Y. Ito, K. Meguro, T. Matsukura, F. Takahashi, H. Matsuoka, H. Ohno, H.
Copyright Year	1966
Abstract	A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM) chip using a 0.2 mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power nonvolatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque writing of 100 ns, and parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances that lead to 40 ns access time.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	109
Ending Page	120
Page Count	12
File Size	3667280
File Format	PDF
ISSN	00189200
Volume Number	43
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Torque Bidirectional control Read-write memory Random access memory Writing Laboratories Indium tin oxide Tunneling Circuits Nonvolatile memory universal memory Bi-directional current write parallelizing direction current read low-power RAM nonvolatile RAM spin-transfer torque TMR
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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