NDLI: 3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach

Content Provider	IEEE Xplore Digital Library
Author	Rogdakis, K. Seoung-Yong Lee Bescond, M. Sang-Kwon Lee Bano, E. Zekentes, K.
Copyright Year	1963
Abstract	Experimental and simulated I-V characteristics of silicon carbide (SiC) nanowire-based field-effect transistors (NWFETs) are presented. SiC NWs were fabricated by using the vapor-liquid-solid mechanism in a chemical vapor deposition system. The diameter of fabricated SiC NWs varied from 60 up to 100 nm while they were some micrometers long. Their I-V characteristics were simulated with SILVACO software, and special attention was paid to explore the role of NW doping level and NW/dielectric interface quality. The fabricated SiC-based NWFETs exhibit a mediocre gating effect and were not switched-off by varying the gate voltage. Based on the simulations, this is a result of the high unintentional doping (estimated at 1times10¹⁹ cm^-3) and the poor NW/dielectric interface quality. Moreover, a homemade algorithm was used to investigate the ideal properties of SiC-based NWFETs in ballistic transport regime, with NW lengths of 5-15 nm and a constant diameter of 4 nm for which the carrier transport is fully controlled by quantum effects. This algorithm self-consistently solves the Poisson equation with the quantum nonequilibrium Green function formalism. In the ballistic regime, devices with undoped SiC NWs exhibit superior theoretical performances (transconductance: ~43.2times10^-6 A/V and I_ON/I_OFF=1.6times10⁵ for a device with 9-nm NW length) based on their simulated characteristics.
Sponsorship	IEEE Electron Devices Society
Starting Page	1970
Ending Page	1976
Page Count	7
File Size	1056059
File Format	PDF
ISSN	00189383
Volume Number	55
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	$\beta$ -silicon carbide (SiC) nanowires (NWs) Drift-diffusion (DD) model field-effect transistor (FET) nonequilibrium Green function formalism (NEGF)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Field-effect transistor based on /spl beta/-SiC nanowire

Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates

Performance Evaluation of III–V Nanowire Transistors

Impact of Precisely Positioned Dopants on the Performance of an Ultimate Silicon Nanowire Transistor: A Full Three-Dimensional NEGF Simulation Study

Surface-Roughness-Limited Mean Free Path in Silicon Nanowire Field Effect Transistors

Investigation of Sensor Performance in Accumulation- and Inversion-Mode Silicon Nanowire pH Sensors

Development of a Vertical Wrap-Gated InAs FET

ZnO Nanowire Field-Effect Transistors

Band Structure Effects in Extremely Scaled Silicon Nanowire MOSFETs With Different Cross Section Shapes

3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach

Similar Documents

Field-effect transistor based on /spl beta/-SiC nanowire

Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates

Performance Evaluation of III–V Nanowire Transistors

Impact of Precisely Positioned Dopants on the Performance of an Ultimate Silicon Nanowire Transistor: A Full Three-Dimensional NEGF Simulation Study

Surface-Roughness-Limited Mean Free Path in Silicon Nanowire Field Effect Transistors

Investigation of Sensor Performance in Accumulation- and Inversion-Mode Silicon Nanowire pH Sensors

Development of a Vertical Wrap-Gated InAs FET

ZnO Nanowire Field-Effect Transistors

Band Structure Effects in Extremely Scaled Silicon Nanowire MOSFETs With Different Cross Section Shapes

3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach