NDLI: A BIST TPG for Low Power Dissipation and High Fault Coverage

Content Provider	IEEE Xplore Digital Library
Author	Seongmoon Wang
Copyright Year	1993
Abstract	This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	777
Ending Page	789
Page Count	13
File Size	536531
File Format	PDF
ISSN	10638210
Volume Number	15
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Power dissipation Circuit faults Circuit testing Test pattern generators Switching circuits Automatic testing Electrical fault detection Fault detection Hardware random pattern testing Built-in self-test (BIST) heat dissipation during test application low power testing power dissipation during test application
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Fault diagnosis for using TPG low power dissipation and high fault coverage

Generation of low power dissipation and high fault coverage patterns for scan-based BIST

On-chip deterministic counter-based TPG with low heat dissipation

LT-RTPG: a new test-per-scan BIST TPG for low switching activity

A Novel BIST TPG for Testing of VLSI Circuits

LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

High defect coverage with low-power test sequences in a BIST environment

BIST hardware generator for mixed test scheme

TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure

A BIST TPG for Low Power Dissipation and High Fault Coverage

Similar Documents

Fault diagnosis for using TPG low power dissipation and high fault coverage

Generation of low power dissipation and high fault coverage patterns for scan-based BIST

On-chip deterministic counter-based TPG with low heat dissipation

LT-RTPG: a new test-per-scan BIST TPG for low switching activity

A Novel BIST TPG for Testing of VLSI Circuits

LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

High defect coverage with low-power test sequences in a BIST environment

BIST hardware generator for mixed test scheme

TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure

A BIST TPG for Low Power Dissipation and High Fault Coverage