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Content Provider | IEEE Xplore Digital Library |
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Author | Dimitrakopoulos, G. Mavrokefalidis, C. Galanopoulos, K. Nikolos, D. |
Copyright Year | 1993 |
Abstract | Single or multibit subword permutations are useful in many multimedia and cryptographic applications. Several specialized instructions have been proposed to handle the required data rearrangements. In this paper, we examine the hardware implementation of the powerful permutation instruction group (GRP). The design of the proposed permutation unit is based on the functionality of sorting networks. Two variants of the sorter-based GRP unit are introduced and analyzed and their energy-delay behavior is investigated using static CMOS implementations in a 130-nm CMOS technology. |
Sponsorship | IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation |
Starting Page | 711 |
Ending Page | 715 |
Page Count | 5 |
File Size | 709873 |
File Format | |
ISSN | 10638210 |
Volume Number | 15 |
Issue Number | 6 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2007-06-01 |
Publisher Place | U.S.A. |
Access Restriction | One Nation One Subscription (ONOS) |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Microprocessors Sorting CMOS technology Cryptography Hardware Software algorithms Circuits Multimedia computing Parallel processing Software performance sorting networks data-rearrangement instructions multimedia processors permutation units |
Content Type | Text |
Resource Type | Article |
Subject | Electrical and Electronic Engineering Software Hardware and Architecture |
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