NDLI: The Potential of FinFETs for Analog and RF Circuit Applications

Content Provider	IEEE Xplore Digital Library
Author	Wambacq, P. Verbruggen, B. Scheir, K. Borremans, J. Dehan, M. Linten, D. De Heyn, V. Van der Plas, G. Mercha, A. Parvais, B. Gustin, C. Subramanian, V. Collaert, N. Jurczak, M. Decoutere, S.
Copyright Year	2004
Abstract	CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2541
Ending Page	2551
Page Count	11
File Size	2808858
File Format	PDF
ISSN	15498328
Volume Number	54
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Radio frequency Performance gain Circuit noise Acoustical engineering Semiconductor device noise Linearity Electrodes Dielectric materials Scalability nanotechnology Electrostatic discharges (ESDs) fin-shaped field-effect transistor (FinFET) mixed analog integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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