NDLI: Timing Recovery for Backplane Ethernet

Content Provider	IEEE Xplore Digital Library
Author	Wei Zhang Spencer, R.R.
Copyright Year	2004
Abstract	The dominant solutions for single-chip multi-port backplane Ethernet transceivers utilize a dual-loop design - a combination of a single master phase-locked loop (PLL) and multiple slave delay-locked loops (DLL). Each transmitter or receiver port has its own DLL, which delays or advances a copy of the master clock from the master PLL to generate its own clock signal for synchronization. The DLLs are typically implemented using current-mode logic phase interpolators. This paper presents an alternative solution to this synchronization problem. Instead of moving the sampling phase, timing recovery is done by changing the group delay of the receiver-side forward equalizer by rotating its tap coefficients. The standard least-mean-square algorithm is used for coefficient rotation. This solution is equivalent to a first-order PLL/DLL, which suffers from steady-state timing offset when there is a frequency offset between the transmitter and the receiver. However, the degradation in performance caused by a frequency offset is significantly reduced by using a coefficient-rotation digital-signal processor capable of detecting and reducing the offset. With a practical frequency accuracy specification of plusmn100 ppm, the improved performance can approach that of the PLL/DLL dual-loop solution.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1711
Ending Page	1723
Page Count	13
File Size	1117967
File Format	PDF
ISSN	15498328
Volume Number	54
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Backplanes Ethernet networks Phase locked loops Delay Transmitters Clocks Frequency synchronization Transceivers Master-slave timing recovery (TR) Asynchronous backplane delay-locked loop (DLL) joint adaptation least-mean-square (LMS) adaptation phase-locked loop (PLL)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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