NDLI: A 144<formula formulatype=inline><tex>$,times,$</tex></formula>144 Current-Mode Image Sensor With Self-Adapting Mismatch Reduction

Content Provider	IEEE Xplore Digital Library
Author	Wong, Y.L. Abshire, P.A.
Copyright Year	2004
Abstract	We present a novel CMOS continuous-current imager that uses nonvolatile floating-gate charge storage in each pixel for automatic cancellation of fixed-pattern noise (FPN) and vignetting artifacts. We demonstrate the ability to reduce image artifacts over a wide range of incident light intensities. Adaptation occurs for each pixel in parallel, using a unique pixel circuit that employs hot-electron injection in stable feedback to accurately match a reference value. The adaptation mechanism stores a reference image, which may be uniform for FPN cancellation or nonuniform for various imaging applications. The design has been fabricated in a commercially available 3-metal, 2-poly 0.5-mum standard CMOS technology. Experimental results confirm the ability to reduce the FPN variance by a factor of 178x at the intensity at which adaptation was performed, and by a factor of 34x over five orders of magnitude of intensity. Adaptation takes as little as 4 s and the 144 times 144 image can be acquired at 0.9 frames/s. During normal operation, the chip consumes 140 muW under standard office lighting conditions at room temperature.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1687
Ending Page	1697
Page Count	11
File Size	2138158
File Format	PDF
ISSN	15498328
Volume Number	54
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image sensors Image storage CMOS technology CMOS image sensors Storage automation Pixel Circuit noise Noise cancellation Feedback circuits Secondary generated hot electron injection error compensation Analog memories automatic programming calibration hot carriers image sensors insulated gate field-effect transistors (FETs)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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