NDLI: Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip

Content Provider	IEEE Xplore Digital Library
Author	Koickal, T.J. Hamilton, A. Su Lim Tan Covington, J.A. Gardner, J.W. Pearce, T.C.
Copyright Year	2004
Abstract	In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal "spiking" signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon
Sponsorship	IEEE Circuits and Systems Society
Starting Page	60
Ending Page	73
Page Count	14
File Size	2215103
File Format	PDF
ISSN	15498328
Volume Number	54
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Neuromorphics Analog circuits Chemical sensors Sensor arrays Adaptive signal processing Array signal processing Biomedical signal processing Chemical and biological sensors Biosensors spike-timing-dependent plasticity (STDP) Analog VLSI electronic nose machine olfaction neuromorphic circuits on-chip learning
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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