NDLI: Statistical timing analysis under spatial correlations

Content Provider	IEEE Xplore Digital Library
Author	Hongliang Chang Sapatnekar, S.S.
Copyright Year	1982
Abstract	Process variations are of increasing concern in today's technologies, and they can significantly affect circuit performance. An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra-die variations, while accounting for the effects of spatial correlations of intra-die parameter variations, is presented. The procedure uses a first-order Taylor series expansion to approximate the gate and interconnect delays. Next, principal component analysis (PCA) techniques are employed to transform the set of correlated parameters into an uncorrelated set. The statistical timing computation is then easily performed with a program evaluation and review technique (PERT)-like circuit graph traversal. The run time of this algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations. The accuracy of the method is verified with Monte Carlo (MC) simulation. On average, for the 100 nm technology, the errors of mean and standard deviation (SD) values computed by the proposed method are 1.06% and -4.34%, respectively, and the errors of predicting the 99% and 1% confidence point are -2.46% and -0.99%, respectively. A testcase with about 17 800 gates was solved in about 500 s, with high accuracy as compared to an MC simulation that required more than 15 h.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1467
Ending Page	1482
Page Count	16
File Size	481125
File Format	PDF
ISSN	02780070
Volume Number	24
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Integrated circuit interconnections Principal component analysis Computational modeling Circuit optimization Algorithm design and analysis Prediction algorithms Probability distribution Delay effects Taylor series VLSI Circuit deep submicron timing analysis
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Weibull-based analytical waveform model

A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations

Path-Based Buffer Insertion

Timing-driven placement for regular architectures

Buffer insertion for noise and delay optimization

Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model

Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's

Interconnect Bundle Sizing Under Discrete Design Rules

Longest-path selection for delay test under process variation

Statistical timing analysis under spatial correlations

Similar Documents

Weibull-based analytical waveform model

A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations

Path-Based Buffer Insertion

Timing-driven placement for regular architectures

Buffer insertion for noise and delay optimization

Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model

Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's

Interconnect Bundle Sizing Under Discrete Design Rules

Longest-path selection for delay test under process variation

Statistical timing analysis under spatial correlations