NDLI: A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

Content Provider	IEEE Xplore Digital Library
Author	Ryckaert, J. Van der Plas, G. De Heyn, V. Desset, C. Van Poucke, B. Craninckx, J.
Copyright Year	1966
Abstract	We propose an all-digital UWB transmitter architecture that exploits the low duty cycle of impulse-radio UWB to achieve ultra-low power consumption. The design supports the IEEE 802.15.4a standard and is demonstrated for its mandatory mode. A digitally controlled oscillator produces the RF carrier between 3 and 10 GHz. It is embedded in a phase-aligned frequency-locked loop that starts up in 2 ns and thus exploits the signal duty cycle that can be as low as 3%. A fully dynamic modulator shapes the BPSK symbols in discrete steps at the 499.2 MHz chip rate as required by the standard. The transmitter can operate in any 499.2 MHz band of the standard between 3.1 and 10 GHz, and the generated signal fulfills the emission spectral mask. The jitter accumulation over a burst is below 6 ps_RMS, which is within specifications. The transmitter was realized in a 1 V 90 nm digital CMOS technology, and its power consumption drawn from a 1 V supply is from 0.65 mW at 3.1 GHz to 1.4 mW at 10 GHz for a 1 Mb/s data rate.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	2860
Ending Page	2869
Page Count	10
File Size	2076338
File Format	PDF
ISSN	00189200
Volume Number	42
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transmitters Energy consumption CMOS technology Digital control Oscillators Radio frequency Frequency locked loops Shape Binary phase shift keying Signal generators ultra-wideband (UWB) IEEE 802.15.4a standard impulse radio phase-locked loops (PLLs) transmitters
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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