NDLI: A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With <formula formulatype=inline><tex>$-$</tex></formula>75 dBc Single-Tone Sensitivity at 100 kHz Offset

Content Provider	IEEE Xplore Digital Library
Author	Khalil, W. Bakkaloglu, B. Kiaei, S.
Copyright Year	1966
Abstract	An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	2758
Ending Page	2765
Page Count	8
File Size	874717
File Format	PDF
ISSN	00189200
Volume Number	42
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase measurement Integrated circuit measurements Clocks Frequency Time measurement Built-in self-test Measurement techniques Jitter Calibration Phase locked loops phase noise Built-in self-test (BIST) jitter phase-locked loops (PLLs)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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