NDLI: Pulsewidth-Modulated <formula formulatype=inline><tex>$Z$</tex></formula>-Source Neutral-Point-Clamped Inverter

Content Provider	IEEE Xplore Digital Library
Author	Poh Chiang Loh Feng Gao Blaabjerg, F. Shi Yun Charmaine Feng Kong Ngai Jamies Soon
Copyright Year	1972
Abstract	This paper presents the careful integration of a newly proposed Z-source topological concept to the basic neutral-point-clamped (NPC) inverter topology for designing a three-level inverter with both voltage-buck and voltage-boost capabilities. The designed Z-source NPC inverter uses two unique X-shaped inductance-capacitance (LC) impedance networks that are connected between two isolated dc input power sources and its inverter circuitry for boosting its AC output voltage. Through the design of an appropriate pulsewidth-modulation (PWM) algorithm, the two impedance networks can be short-circuited sequentially (without shooting through the inverter full DC link) for implementing the ldquonearest-three-vectorrdquo modulation principle with minimized harmonic distortion and device commutations per half carrier cycle while performing voltage boosting. With only a slight modification to the inverter PWM algorithm and by short-circuiting the two impedance networks simultaneously, the designed NPC inverter, with no requirement for deadtime delay, can also be operated with a completely eliminated common-mode voltage. Implementation wise, a detailed vectorial analysis interestingly shows that the same generic set of carrier-based modulation expressions can be used for controlling the -source two-level inverter and NPC inverter with and without reduced common-mode switching. All findings presented in this paper have been confirmed in simulation and experimentally using an implemented laboratory prototype.
Sponsorship	IEEE Industry Applications Society
Starting Page	1295
Ending Page	1308
Page Count	14
File Size	2730424
File Format	PDF
ISSN	00939994
Volume Number	43
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pulse inverters Pulse width modulation inverters Voltage Impedance Boosting Algorithm design and analysis Network topology Circuit topology Harmonic distortion Laboratories $Z$-source inverters Buck–boost common-mode voltage neutral-point-clamped (NPC) inverters pulsewidth modulation (PWM)
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Control and Systems Engineering Electrical and Electronic Engineering

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Comparative Evaluation of Pulsewidth Modulation Strategies for Z-Source Neutral-Point-Clamped Inverter

Space-Vector-Based Hybrid Pulsewidth Modulation Techniques for a Three-Level Inverter

Analytical Closed-Form Expressions for Harmonic Distortion Corresponding to Novel Switching Sequences for Neutral-Point-Clamped Inverters

Time-Offset Injection Method for Neutral-Point AC Ripple Voltage Reduction in a Three-Level Inverter

Trans-Z-source and Γ-Z-source neutral-point-clamped inverters

Detection Method for Open-Circuit Fault in Neutral-Point-Clamped Inverter Systems

Space-Vector Pulsewidth Modulation for Three-Level NPC Converter With the Neutral Point Voltage Control

Three Phase Three-Level PWM Switched Voltage Source Inverter With Zero Neutral Point Potential

Hybrid PWM Strategy of SVPWM and VSVPWM for NPC Three-Level Voltage-Source Inverter

Pulsewidth-Modulated $Z$-Source Neutral-Point-Clamped Inverter

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