NDLI: A mesochronous pipelining scheme for high-performance digital systems

Content Provider	IEEE Xplore Digital Library
Author	Tatapudi, S.B. Delgado-Frias, J.G.
Copyright Year	2004
Abstract	A novel mesochronous pipelining scheme is described in this paper. In this scheme, data and clock travel together. At any given time a pipeline stage could be operating on more than one data wave. The clock period in the proposed pipeline scheme is determined by the pipeline stage with largest difference between its minimum and maximum delays. This is a significant performance gain compared to conventional pipeline scheme where clock period is determined by the stage with the largest delay. A detailed analysis of the clock period constraints is provided to show the performance gains and Speedup of mesochronous pipelining over other pipelining schemes. Also, the number of pipeline stages and pipeline registers is small. The clock distribution scheme is simple in the mesochronous pipeline architecture. An 8 /spl times/ 8-bit carry-save adder multiplier has been implemented in mesochronous pipeline architecture using modest TSMC 180-nm (drawn length 200 nm) CMOS technology. The multiplier architecture and simulation results are described in detail in this paper. The pipelined multiplier is able to operate on a clock period of 350 ps (2.86 GHz). This is a Speedup of 1.7 times over conventional pipeline scheme, with fewer pipeline stages and pipeline registers.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1078
Ending Page	1088
Page Count	11
File Size	1152534
File Format	PDF
ISSN	15498328
Volume Number	53
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Digital systems Clocks Propagation delay Registers Performance gain CMOS technology Logic Synchronization Uncertainty register delays High performance mesochronous pipeline multiplier pipelined system
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A mesochronous pipeline scheme for high performance low power digital systems

Designing pipelined systems with a clock period approaching pipeline register delay

Designing pipelined systems with a clock period approaching pipeline register delay.

8×8-Bit multiplier designed with a new wave-pipelining scheme

A pipelined multiplier using a hybrid wave-pipelining scheme.

A high performance hybrid wave-pipelined multiplier

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

A Reduced Clock Delay Approach for High Performance Mesochronous Pipeline

Design and realization of high-performance wave-pipelined 8/spl times/8 b multiplier in CMOS technology

A mesochronous pipelining scheme for high-performance digital systems

Similar Documents

A mesochronous pipeline scheme for high performance low power digital systems

Designing pipelined systems with a clock period approaching pipeline register delay

Designing pipelined systems with a clock period approaching pipeline register delay.

8×8-Bit multiplier designed with a new wave-pipelining scheme

A pipelined multiplier using a hybrid wave-pipelining scheme.

A high performance hybrid wave-pipelined multiplier

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

A Reduced Clock Delay Approach for High Performance Mesochronous Pipeline

Design and realization of high-performance wave-pipelined 8/spl times/8 b multiplier in CMOS technology

A mesochronous pipelining scheme for high-performance digital systems