NDLI: Design of a 128-mb SOI DRAM using the floating body cell (FBC)

Content Provider	IEEE Xplore Digital Library
Author	Ohsawa, T. Fujita, K. Hatsuda, K. Higashi, T. Shino, T. Minami, Y. Nakajima, H. Morikado, M. Inoh, K. Hamamoto, T. Watanabe, S. Fujii, S. Furuyama, T.
Copyright Year	1966
Abstract	A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	135
Ending Page	145
Page Count	11
File Size	1443892
File Format	PDF
ISSN	00189200
Volume Number	41
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Capacitors System-on-a-chip Contacts Immune system Material storage Research and development Degradation Charge pumps Capacitance system-on-a-chip 1T-DRAM capacitorless DRAM embedded memory floating body cell silicon-on-insulator technology
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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