NDLI: Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model

Content Provider	IEEE Xplore Digital Library
Author	Jiang Hu Sapatnekar, S.S.
Copyright Year	1982
Abstract	To improve the performance of critical nets where both timing and wire resources are stringent, we integrate buffer insertion and driver sizing separately with non-Hanan optimization and propose two algorithms: simultaneous buffer insertion and non-Hanan optimization (BINO) and full-plane AWE routing with driver sizing (FAR-DS). For BINO, we consider the realistic situation that buffer locations are restricted to a limited set of available spaces after cell placement. The objective of BINO is to minimize a weighted sum of wire and buffer costs subject to timing constraints. To achieve this objective, we suggest a greedy algorithm that considers two operations independently: iterative buffer insertion and iterative buffer deletion. Both are conducted simultaneously with non-Hanan optimization until the improvement is exhausted. For FAR-DS, we investigate the curvature property of the sink delay as a function of both connection location and driver stage ratio in a two-dimensional (2-D) space. The objective of FAR-DS is to minimize a weighted sum of wire and driver cost while ensuring that the timing constraints are satisfied. Based on the curvature property, we search for the optimal solution in the continuous 2-D space. In both BINO and FAR-DS, a fourth-order AWE delay model is employed to assure the quality of optimization. Experiments of BINO and FAR-DS on both integrated circuit and MCM technologies showed significant cost reductions compared with SERT and MVERT in addition to making the interconnect to satisfy timing constraints.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	446
Ending Page	458
Page Count	13
File Size	363424
File Format	PDF
ISSN	02780070
Volume Number	19
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Timing Wire Costs Integrated circuit interconnections Delay Space technology Routing Greedy algorithms Two dimensional displays
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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