NDLI: Integrated hardware and software for improved flatness measurement with ATC4.1 flip-chip assembly case study

Content Provider	IEEE Xplore Digital Library
Author	Hai Ding Ume, I.C. Jian Zhang Baldwin, D.F.
Copyright Year	1963
Abstract	Over the past four decades, microelectronic packaging technology has evolved from peripheral, through-hole, and bulk configurations to area-array, surface-mount, and small-profile ones. Among these approaches, flip-chip attachment has become the most favorable choice for its large input/output capabilities and short signal path distributions. Given the prediction that the chip size and power of a single chip package will increase dramatically, substrate warpage of flip-chip packages during assembly and usage has become a major concern. Warpage could cause misalignment between the chip and the substrate, prevent the solder balls from making contact with the substrate flip-chip pads during the reflow soldering process, and induce crack nucleation at the board underfill interface during long-term usage. In this paper, the authors developed an integrated large-area shadow moire system for measuring small and large board and chip package warpage. The hardware is designed to carry out warpage measurement with a resolution on the order of micrometers. Combined with software, the integrated system is fully automated and highly accurate. For the case study, the system is used to characterize the substrate warpage of flip-chip on organic board assemblies. Warpage of substrates at the initial bare-board stage, post-reflow, and post-underfill is measured at room temperatures. It is found that by properly selecting initially warped substrates, post-reflow and post-underfill warpage can be reduced. In addition, warpage measurements at elevated temperatures during thermal cycling and power cycling show that power cycling poses a smaller impact on substrate warpage.
Sponsorship	IEEE Instrumentation and Measurement Society Bureau international des poids et mesures IEEE International Bureau of Weights and Measures (BIPM) URSI NBS Agency Ind. Sci. & Technol., Min. Int. Trade & Ind. Sci. Council Japan International Union of Pure and Applied Physics (IUPAP) NIST NRCC National Conference of Standards Laboratories (NCSL) Allen Osborne Associates Andeen-Hagerling, Inc. Ballantine Lab. Inc. Clarke-Hess Communications Research Corp. Fluke Corporation Guildline Instruments Hewlett-Packard Co. Julie Res. Lab. Inc. Keithley Instruments, Inc. Measurements International Ltd. Canada QuadTech Inc. Quantum Design Inc. Rotek Instrum. Corp. Tegam Inc. Tektronix Inc
Starting Page	1898
Ending Page	1904
Page Count	7
File Size	1069870
File Format	PDF
ISSN	00189456
Volume Number	54
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Software measurement Assembly Packaging Temperature measurement Semiconductor device measurement Microelectronics Surface-mount technology Reflow soldering Software systems thermal warpage Assembly test chip (ATC) flip-chip high-density interconnect (HDI) board infrared (IR) and convection oven phase stepping shadow moireÉ surface-mount assembly temperature cycling
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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Model for Inverse Determination of Process and Material Parameters for Control of Package-on-Package Warpage

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