NDLI: Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices

Content Provider	IEEE Xplore Digital Library
Author	Numata, T. Mizuno, T. Tezuka, T. Koga, J. Takagi, S.
Copyright Year	1963
Abstract	This paper presents a quantitative study on the device design for the control of threshold-voltage and the suppression of short-channel effects (SCEs) in ultrathin strained-silicon-on-insulator (strained-SOI) CMOSFETs in the sub-100-nm regime. A two-dimensional device simulation is used for this purpose, with emphasis on the impact of band offset in Si/SiGe heterostructures. For the control of threshold-voltage, the combination of the gate work function and the back gate bias is needed to obtain appropriate values of threshold-voltage in n- and p-channel MOSFETs and to suppress SiGe buried channels in p-channel MOSFETs with thicker strained-Si layers. Regarding SCEs, the importance and the necessity of thin SiGe layers are pointed out from the viewpoint of the influence of the higher permittivity of SiGe layers. It is shown that the SCEs of strained-SOI MOSFETs with thinner SiGe layers are almost the same level as those of unstrained-SOI.
Sponsorship	IEEE Electron Devices Society
Starting Page	1780
Ending Page	1786
Page Count	7
File Size	508906
File Format	PDF
ISSN	00189383
Volume Number	52
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS integrated circuits Silicon Silicon on insulator technology MOSFET circuits Integrated circuit design Work function Germanium alloys Silicon alloys strained-silicon (strained-Si) MOSFETs silicon-on-insulator (SOI)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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