NDLI: On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries

Content Provider	IEEE Xplore Digital Library
Author	Hatzopoulos, A.T. Tassis, D.H. Hastas, N.A. Dimitriadis, C.A. Kamarinos, G.
Copyright Year	1963
Abstract	An analytical on-state drain current model of large-grain polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented, based on the carrier transport through latitudinal and longitudinal grain boundaries. The model considers an array of square grains in the channel, with the current flowing along the longitudinal grain boundaries or through the grains and across the latitudinal grain boundaries. Application of the proposed model to excimer lased annealed polysilicon TFTs reveals that, at low gate voltages in the moderate inversion region, the longitudinal grain boundaries influence the effective carrier mobility and the drain current. As the gate voltage increases, the latitudinal grain boundaries have larger impact to the current flow due to reduction of the potential barrier at the grain boundaries. The effect of the laser energy density on the quality of the grains and grain boundaries is investigated.
Sponsorship	IEEE Electron Devices Society
Starting Page	1727
Ending Page	1733
Page Count	7
File Size	454985
File Format	PDF
ISSN	00189383
Volume Number	52
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thin film transistors Laser annealing Excimer lasers Silicon polycrystalline silicon thin-film transistors (polysilicon TFTs) Grain boundaries modeling on-state current
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Polycrystalline Silicon Thin-Film Transistor Using Xe Flash-Lamp Annealing

High-Performance Polycrystalline-Silicon Nanowire Thin-Film Transistors With Location-Controlled Grain Boundary via Excimer Laser Crystallization

Large on/off current ratio and low leakage current poly-Si TFTs with multichannel structure

Low-Temperature Fabricated TFTs on Polysilicon Stripes

Bridged-Grain Solid-Phase-Crystallized Polycrystalline-Silicon Thin-Film Transistors

Deep Analysis of the Geometric Component in Charge Pumping of Polycrystalline Silicon Thin-Film Transistors

Protrusions of Super Grains Formed by Ultrashort Xe Flash-Lamp Annealing of Amorphous Silicon and Its Effect on the Performances of Thin-Film Transistors

The Channel Length Extension in Poly-Si TFTs With LDD Structure

An Effective Channel Mobility-Based Analytical On-Current Model for Polycrystalline Silicon Thin-Film Transistors

On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries

Similar Documents

Polycrystalline Silicon Thin-Film Transistor Using Xe Flash-Lamp Annealing

High-Performance Polycrystalline-Silicon Nanowire Thin-Film Transistors With Location-Controlled Grain Boundary via Excimer Laser Crystallization

Large on/off current ratio and low leakage current poly-Si TFTs with multichannel structure

Low-Temperature Fabricated TFTs on Polysilicon Stripes

Bridged-Grain Solid-Phase-Crystallized Polycrystalline-Silicon Thin-Film Transistors

Deep Analysis of the Geometric Component in Charge Pumping of Polycrystalline Silicon Thin-Film Transistors

Protrusions of Super Grains Formed by Ultrashort Xe Flash-Lamp Annealing of Amorphous Silicon and Its Effect on the Performances of Thin-Film Transistors

The Channel Length Extension in Poly-Si TFTs With LDD Structure

An Effective Channel Mobility-Based Analytical On-Current Model for Polycrystalline Silicon Thin-Film Transistors

On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries